Study of the effects of SEU-induced faults on a pipeline protected microprocessor

This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault manifestation, and the behavior of latent faults

Efficient protection of the pipeline core for safety-critical processor-based systems

The increasing number of safety-critical commercial applications has generated a need for components with high levels of reliability. As CMOS process sizes continue to shrink, the reliability of ICs is negatively affected since they become more sensitive to transient faults. New circuit designs must take this fact into consideration, and incorporate adequate protection against the effects of transient faults. This paper presents a novel method for protecting the pipelined execution unit of an embedded processor. It is based on a self-configured architecture with hybrid redundancy that can mask single and multiple errors, which can occur on storage elements due to transient or permanent faults. This concept can be easily applied to any processing architecture of this nature with a high safety integrity level. Results from error-injection experiments are also reported that show that this design can maintain a non-interrupted and failure-free operation under single and double errors with a probability that exceeds 99.4%

A fault tolerant micoarchitecure for safety-related automotive control

The successful use of fly-by-wire systems in aviation along with the positive experience of drive-by-wire systems with mechanical backup for braking and power steering have led to the development of complete drive-by-wire systems that reduce the cost of a vehicle, are lighter and provide better passive safety to the passenger. These systems have the form of a distributed, real-time embedded system. Similar architectures can be found in other safetycritical and mission-critical applications in avionics, as mentioned before, medical equipment, and the industrial sector. The advances in embedded system technology has enabled designers to implement low-cost and small form factor electronics. However shrinking CMOS technologies are facing considerable reliability problems since they become more sensitive to transient faults. This thesis investigates the application of traditional methods for the development of safety critical computer systems and their application on single-chip devices. The contributions of this work are briefly summarised as follows: • The development of a novel fault-tolerant architecture for protecting the processor core. • Methods for performing fault-injection experiments on embedded processor architectures. • Fault-models for multiple faults on digital systems with the use of statistical distributions. • An extensive study of a processor's behaviour under the presence of faults within its pipelined execution unit